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/*                  Atmel Microcontroller Software Support                      */
/*                       SAM Software Package License                           */
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/* Copyright (c) 2014, Atmel Corporation                                        */
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#ifndef _SAM_RTC_INSTANCE_
#define _SAM_RTC_INSTANCE_

/* ========== Register definition for RTC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
  #define REG_RTC_CR                       (0x400E1860U) /**< \brief (RTC) Control Register */
  #define REG_RTC_MR                       (0x400E1864U) /**< \brief (RTC) Mode Register */
  #define REG_RTC_TIMR                     (0x400E1868U) /**< \brief (RTC) Time Register */
  #define REG_RTC_CALR                     (0x400E186CU) /**< \brief (RTC) Calendar Register */
  #define REG_RTC_TIMALR                   (0x400E1870U) /**< \brief (RTC) Time Alarm Register */
  #define REG_RTC_CALALR                   (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */
  #define REG_RTC_SR                       (0x400E1878U) /**< \brief (RTC) Status Register */
  #define REG_RTC_SCCR                     (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */
  #define REG_RTC_IER                      (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */
  #define REG_RTC_IDR                      (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */
  #define REG_RTC_IMR                      (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */
  #define REG_RTC_VER                      (0x400E188CU) /**< \brief (RTC) Valid Entry Register */
  #define REG_RTC_TSTR0                    (0x400E1910U) /**< \brief (RTC) TimeStamp Time Register 0 */
  #define REG_RTC_TSDR0                    (0x400E1914U) /**< \brief (RTC) TimeStamp Date Register 0 */
  #define REG_RTC_TSSR0                    (0x400E1918U) /**< \brief (RTC) TimeStamp Source Register 0 */
  #define REG_RTC_TSTR1                    (0x400E191CU) /**< \brief (RTC) TimeStamp Time Register 1 */
  #define REG_RTC_TSDR1                    (0x400E1920U) /**< \brief (RTC) TimeStamp Date Register 1 */
  #define REG_RTC_TSSR1                    (0x400E1924U) /**< \brief (RTC) TimeStamp Source Register 1 */
  #define REG_RTC_WPMR                     (0x400E1944U) /**< \brief (RTC) Write Protection Mode Register */
  #define REG_RTC_VERSION                  (0x400E195CU) /**< \brief (RTC) Version Register */
#else
  #define REG_RTC_CR      (*(__IO uint32_t*)0x400E1860U) /**< \brief (RTC) Control Register */
  #define REG_RTC_MR      (*(__IO uint32_t*)0x400E1864U) /**< \brief (RTC) Mode Register */
  #define REG_RTC_TIMR    (*(__IO uint32_t*)0x400E1868U) /**< \brief (RTC) Time Register */
  #define REG_RTC_CALR    (*(__IO uint32_t*)0x400E186CU) /**< \brief (RTC) Calendar Register */
  #define REG_RTC_TIMALR  (*(__IO uint32_t*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */
  #define REG_RTC_CALALR  (*(__IO uint32_t*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */
  #define REG_RTC_SR      (*(__I  uint32_t*)0x400E1878U) /**< \brief (RTC) Status Register */
  #define REG_RTC_SCCR    (*(__O  uint32_t*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */
  #define REG_RTC_IER     (*(__O  uint32_t*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */
  #define REG_RTC_IDR     (*(__O  uint32_t*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */
  #define REG_RTC_IMR     (*(__I  uint32_t*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */
  #define REG_RTC_VER     (*(__I  uint32_t*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */
  #define REG_RTC_TSTR0   (*(__I  uint32_t*)0x400E1910U) /**< \brief (RTC) TimeStamp Time Register 0 */
  #define REG_RTC_TSDR0   (*(__I  uint32_t*)0x400E1914U) /**< \brief (RTC) TimeStamp Date Register 0 */
  #define REG_RTC_TSSR0   (*(__I  uint32_t*)0x400E1918U) /**< \brief (RTC) TimeStamp Source Register 0 */
  #define REG_RTC_TSTR1   (*(__I  uint32_t*)0x400E191CU) /**< \brief (RTC) TimeStamp Time Register 1 */
  #define REG_RTC_TSDR1   (*(__I  uint32_t*)0x400E1920U) /**< \brief (RTC) TimeStamp Date Register 1 */
  #define REG_RTC_TSSR1   (*(__I  uint32_t*)0x400E1924U) /**< \brief (RTC) TimeStamp Source Register 1 */
  #define REG_RTC_WPMR    (*(__IO uint32_t*)0x400E1944U) /**< \brief (RTC) Write Protection Mode Register */
  #define REG_RTC_VERSION (*(__I  uint32_t*)0x400E195CU) /**< \brief (RTC) Version Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#endif /* _SAM_RTC_INSTANCE_ */
